1. Field of the Invention
The present invention relates to a digital phase-locked loop and a phase/frequency detector module thereof and, more particularly, to a multi-mode digital phase-locked loop with short lock time and a phase/frequency detector module of simultaneously outputting the frequency error and phase error.
2. Description of Related Art
A phase-locked loop (PLL) is a device that generates an output signal to match in phase the frequency of an input signal and is an indispensable component in the design of communication systems. A PLL takes an original clock signal, which may contain a lot of noise, and generates a cleaner clock signal with higher signal-to-noise ratio (SNR) or a new clock signal with different frequency. Besides, a PLL, when applied in communication systems, is used in signal synchronization for clock recovery with respect to the signals received. As the technology of the semiconductor process advances rapidly, many components of communication systems have been assembled and implemented on integrated circuits, which meets manufacturing requirements of low costs, fast production, and miniaturization for communicating devices so that the communicating devices are made widely accessible in our daily life. Therefore, a single chip of integrated circuits that incorporates the PLL component has become a trend in the design of communication systems, as we already saw in most of existing consumer products.
In a convectional PLL design, there exists a certain design limitation between the frequency of the input reference clock signal and the loop bandwidth of the PLL. For example, if a frequency divider is not included at the input stage, the loop bandwidth, ideally, should not be more than one tenth of the frequency of the reference clock signal, and thus the loop bandwidth should be imposed an upper limit of frequency when the frequency of the input reference clock signal is at a low value. In prior-art analog PLL devices, because the frequency of the loop bandwidth is directly related to the resistance and capacitance of the loop filter, the resistance and capacitance may become substantially large when the loop bandwidth is low, and it may be adversely impossible to incorporate such resistors and capacitors with other circuits of the PLL component into a single chip, thereby inevitably increasing circuit dimensions and costs.
Moreover, in an analog PLL, when the frequency of the loop bandwidth is at a low value, the leakage current, caused by devices with large dimensions, may further result in a slower PLL response speed, that is, a longer lock time. Because it is not easy to adopt a multi-mode design in an analog PLL, for example, selecting between the phase-locked mode and frequency-locked mode, the lock time required before an analog PLL is operable may tend to be long. Further, the charge pump unit of the loop filter may cause a mismatch, due to changes of process variation, operating temperature, and the like, between the current of the top current source and the current of the down current source, resulting in an offset on the output frequency or the output phase. Still, an analog PLL finds it difficult to share design parameters among different processes; therefore, a re-design of parameters is necessary when converting processes, and a long simulation time, which is required in an analog PLL, may also cause higher design costs. Finally, the loop in an analog PLL, during activation, should always be maintained, making it not possible to trade off between system performance and power consumption by employing multiple power saving modes and to provide, depending on current system requirements, more flexibility by switching between operating modes.
The advent of semiconductor process technology has made the concept of digital signal processing more acceptable in terms of costs and performance. A digital PLL is thus developed based on the concept of digital signal process. Prior-art digital PLL designs include a time-to-digital converter (TDC) to convert analog-based time into digital data. A digital PLL is designed to easily, compared to an analog PLL, support multi-mode design, modes of which may include the free-running mode where only the digitally controlled oscillator (DCO) is activated and the fast-recovered mode where the result obtained by locking the previous event serves as the starting point of the current event. A digital PLL is able to switch between, depending on current system requirement, different operating modes so as to achieve optimized balance between system performance and power consumption. However, for prior-art digital PLLs, the TDC circuit requires more area and power consumption, and multi-mode digital PLLs may need different circuit blocks to operate under different operating modes, for example, a frequency detector for frequency-locked function or a phase/frequency detector (PFD) for phase-locked function and a frequency divider are needed in the digital PLL device. In addition, a multi-modulus divider (MMD) is required to support the mode of fractional-N PLL (FNPLL). In prior-art PFDs, the bang-bang PFD is the PFD type that consumes least area, but the bang-bang PFD has longer lock time and cannot be applied to the design of the frequency-locked loop (FLL) and the FNPLL.
Referring to Taiwan Patent No. I363499 in which a digital PLL is disclosed. In the invention, the TDC module 102 has a complicated circuit architecture, so an error protection method with respect to the TDC is provided. To support the mode of FNPLL, the invention also includes a complex MMD circuit and a delta-sigma modulator (DSM) on the feedback path, contributing to the complexity of the circuit architecture. The added complexity, however, introduces parasite effect in the circuit and thus limits the operation speed of the PLL.